1. Field of the Invention
The present invention relates to a high voltage generator, and more particularly to a high voltage generator for a semiconductor device which detects a falling of a high voltage level of the device below a voltage level of a power source and then enables the fallen high voltage level to recover to the voltage level of a power source.
2. Description of the Prior Art
FIG. 1A is a block diagram illustrating a conventional high voltage generator.
As shown in FIG. 1A, the high voltage generator includes a high voltage level detector 101, a high voltage pump 102 and an NMOS transistor 10.
The high voltage level detector 101 compares a high voltage VPP with a reference voltage VREFC and judges whether or not the high voltage VPP has a higher level than that of the reference voltage VREFC. When the high voltage VPP has a lower level than that of the reference voltage VREFC, the high voltage level detector 101 outputs an output signal PPE of a high level, thereby enabling the high voltage pump 102.
As generally known in the art, the high voltage pump 102 includes a ring oscillator and a pumping circuit. A detailed circuit of the high voltage pump 102 is well known to those skilled in the art, so detailed description thereof will be omitted.
An output terminal of the high voltage pump 102 is connected to the source of the transistor 10, and both of the drain and the gate of the transistor 10 are connected to the power supply voltage VDD.
FIG. 1B is a circuit illustrating a conventional high voltage detector 101.
In FIG. 1B, a voltage level of a reference voltage VREFC is decided as follow:{R2/(R1+R2)}*VPP−target=VREFC
Herein, the ‘VPP−target’ represents the target value of the high voltage desired by a user.
Therefore, when the voltage level of the high voltage has a lower value than the target value of the high voltage, the output signal PPE of the high voltage level detector becomes a high level, thereby operating the high voltage pump.
FIG. 2 is a graph for exampling relation among the power supply voltage VDD, the high voltage VPP and the reference voltage VREFC shown in FIGS. 1A and 1B.
In FIG. 2, region ‘(1)’ represents a state just after the power supply voltage is applied, region ‘(2)’ represents a normal operation region in which the power supply voltage VDD exceeds a predetermined level, and region ‘(3)’ represents a region in which the power supply voltage is very high, in which region ‘(3)’ is typically employed when a burn-in test is performed.
As shown in regions ‘(1)’ and ‘(3)’ in FIG. 2, there are sections in which the high voltage VPP output from the conventional high voltage generator is lower than the power supply voltage VDD due to the transistor 10 shown in FIG. 1A. That is, there is no problem when the high voltage VPP is higher than the power supply voltage VDD. However, when the high voltage VPP is lower than the power supply voltage VDD, the voltage of the source (i.e., an output terminal of the high voltage pump) of the transistor becomes ‘VDD-Vth’ (herein, ‘Vth’ is a threshold voltage) due to the effects of the transistor 10 having the diode property, thereby causing a problem.
In this case, that is, when the high voltage VPP is lower than the power supply voltage VDD, a latch-up phenomenon happens in a PMOS transistor which is located in a memory cell array region of a memory device using the high voltage VPP as a bulk voltage.